Lead Member Technical Staff

At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. Were excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey!

This is the Role

• Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis.
• Guide and lead others toward successful project completion by innovating and implementing powerful solutions.
• Collaborate with a hardworking team of experts.

Must-Have Requirements

• B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5- 8 years of experience in software development.
• Validated understanding of C/C++, algorithms, and data structures.
• Demonstrate excellent problem-solving and analytical skills.
• Lead and encourage the team with your expertise.

Great to Have Experience in:

• You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power.
• Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power.
• Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL.