- Review SerDes standards to develop analog sub-block design specifications
- Define and refine circuit architectures to meet power, area, and performance goals
- Devise design and verification strategies leveraging advanced simulation tools
- Supervise physical layout to manage parasitics, device stress, and variability
- Present simulation data for internal and customer-facing reviews
- Document design methodologies, features, and test strategies
- Support electrical characterization and propose post-silicon design updates
The Impact You Will Have:
- Drive innovation in high-speed analog circuit design for SerDes IP
- Ensure optimal trade-offs in power, area, and performance
- Enhance reliability and manufacturability of analog sub-blocks
- Support successful integration of SerDes IP into customer solutions
- Contribute to best practices in analog design and simulation within the team
- Influence product development strategies with expert design knowledge
What You'll Need:
- BE with 8+ years or MTech with 6+ years of relevant experience in Electrical/Computer Engineering
- Strong expertise in transistor-level CMOS circuit design and analog design fundamentals
- Experience in designing SerDes sub-circuits like PLLs, TX, RX, CDR, etc.
- Understanding of ESD protection, custom digital design, and high-speed logic
- Familiarity with reliability concerns such as EM, IR drop, and aging
- Proficient with schematic/layout tools and SPICE-based simulators
- Knowledge of Verilog-A for behavioral modeling and scripting in TCL, Perl, Python, or MATLAB
