Lead DFT Engineer
Lead DFT Engineer
AMD Telecom- Posted a day ago
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Job Description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
Lead DFT Engineer
The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
Key Responsiblities
ACADEMIC CREDENTIALS:
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.
This posting is for an existing vacancy.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
Lead DFT Engineer
- THE ROLE:
- As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the DFT Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success.
The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
Key Responsiblities
- Experience with 7+ Years of Strong understanding on Scan Architecture and Scan features
- Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation
- GLS, Timing and Power Aware Simulations
- Test coverage and test cost reduction analysis
- Yield Analysis & Debug for Design root cause & Recovery
- Post Silicon Bring Up: Planning, Co-ordination, and Execution
- DFT Silicon bring up expertise from across tech various nodes
- Extensive Silicon Debug for Phasing closure and production enablement
- Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
- Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
ACADEMIC CREDENTIALS:
- Bachelor's or master's degree in Electronics/VLSI/Electrical Engineering
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.
This posting is for an existing vacancy.
More Info
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Key Skills
Stuck at Transition ATPG
DFT Silicon bring up expertise
Yield Analysis Debug
Test cost reduction analysis
VCS simulation tool
Scan Architecture
GLS Timing and Power Aware Simulations
IDDQ Pattern Generation
Synopsys Tetramax
SOC Tape-Outs
Verilog RTL design
DFTMAX
ATPG pattern generation
Mentor testkompress
Post Silicon Bring Up Planning
Scan features
About Company
Skills:
MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools
Skills:
scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis
Skills:
Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Scan insertion and compression, DFT architecture planning, Boundary scan IEEE 1149.1 1149.6 IJTAG 1687, MBIST, Fault grading, ATPG pattern generation, Logic BIST insertion and validation, Synthesis flows, Rtl Design, Sta
Skills:
Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning, silicon debug, Synopsys Tetramax, SOC Tape-Outs, DFTMAX