Lead DFT Engineer

KEY RESPONSIBILITIES:  

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases 
• Estimate the time required to write the new feature tests and any required changes to the test environment 
• Build the directed and random verification tests 
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements 

PREFERRED EXPERIENCE:  

• Proficient in IP level ASIC verification 
• Proficient in debugging firmware and RTL code using simulation tools  
• Proficient in using UVM test benches and working in Linux and Windows environments 
• Experienced with Verilog, System Verilog, C, and C++   
• Graphics pipeline knowledge 
• Developing UVM based verification frameworks and test benches, processes and flows 
• Automating workflows in a distributed compute environment.   
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process 
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform 
• Good understanding and hands-on experience in the UVM concepts and System Verilog language 
• Good working knowledge of System C and TLM with some related experience.   
• Scripting language experience: Perl, Ruby, Make file, shell preferred.   
• Exposure to leadership or mentorship is an asset 
• Desirable assets with prior exposure to video codec system or other multimedia solutions.   

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1