DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm

PCS, Perl, Python, Tcl, reusable verification infrastructure, PHY link protocols, UVM environment development, high-speed interface verification, Uvm, systemverilog, Ethernet MAC, functional coverage closure, Ethernet protocol compliance verification, packet processing, complex protocol debug, SerDes controller validation, SVA, error handling

Unix, Makefile, Shell, Linux, Perl, Verilog, automation, Python, Scripting, System Verilog, Synthesis, front-end flows, ip design, wireless DSP, high-speed design techniques, VHDL

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design