Lead Design Engineer

Responsibilities

Logic Design Role (RTL Design):

• Develop RTL implementations for microprocessor cores, multiprocessor subsystems, and peripherals using Verilog.
• Define and implement micro-architecture for Xtensa processors.
• Perform simulation, debugging, synthesis, place and route, and timing/area/power closure using EDA tools.
• Develop and execute test plans, functional diagnostics, and debug design issues.
• Analyze functional and code coverage to improve design quality.
• Collaborate with Design Verification and EDA teams for integration and closure activities.

Design Verification Role:

• Develop verification environments for microprocessor cores and subsystems.
• Create test plans, UVM-based verification components, SystemVerilog Assertions (SVA), and functional coverage models.
• Write assembly-level diagnostics for validation of CPU/DSP functionality.
• Debug functional failures across RTL, simulation, and system-level environments.
• Perform coverage analysis and improve verification completeness.
• Work closely with RTL design and EDA teams for issue resolution and sign-off.