Lead Design Engineer
Search Jobs
Search by job, company or skills
Search by job, company or skills
Role Overview:
The DV Architect is a senior technical leadership role responsible for the strategic vision and infrastructure of verification for next-generationTensilica advanced CPU coresand configurable processors. You will define the methodologies that ensure the functional integrity of highly complex instruction set architectures (ISA).
Key Responsibilities:
Methodology Strategy:Define and own the long-term DV architecture, focusing on scalability across multiple processor variants and generations.
Verification Infrastructure:Architect simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
Advanced Verification:Champion the integration of formal verification, and AI-driven coverage analysis.
Cross-Functional Collaboration:Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
Mentorship:Provide technical direction and set the standard for quality and metric-driven verification (MDV) across global teams.
Required Qualifications:
B.Tech/M.Tech in ECE with 4 to 8 years of experience in SoC/CPU/DSP verification.
Deep expertise inSystemVerilog/UVMandC/C++for architectural modeling.
Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com . Privacy Policy: Job ApplicantIf you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) . E-VerifyCadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify(64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Job ID: 147007205
Skills:
Assembly Language, Unix Shell, Verilog, Tcl, Python, Perl, Uvm, SVA, systemverilog, C Language
Skills:
Unix Shell, Tcl, Python, Perl, Synthesis, ASIC Design Flow, Innovus, Timing Analysis, Cadence EDA tools, Tempus, formal verification, Voltus, Genus, Physical Designing, power analysis
Skills:
Dac, Uart, Usb, Verilog, Ethernet, Can, Spi, Pcie, Analog IPs, systemverilog, EDA Tools, SVA, assertions, power-aware simulations, security IPs, SoC-level verification, eSPI, Cadence Xcelium, Uvm, UPF, PLLs, gate-level simulations, ADC, Synopsys VCS, low-power verification, functional coverage, I²C, constrained-random verification, Flash Memory, ARM-based microcontrollers
Skills:
telemetry , Python, Analog Mixed-Signal Design, Stability Compensation, Precision Circuits, Advanced CMOS Processes, Monte Carlo Aging, Spectre, Noise PSRR, Cadence Virtuoso, PVT Mismatch Corners, Variation Reliability
