Tcl, Makefile, static timing analysis, python, Perl, ASIC design flow, EM IR crosstalk analysis, Dfm, Physical Verification, Innovus, Tempus, Cadence EDA tools, hierarchical physical design strategies, low power design, Voltus, formal verification, Tk, Dft, Genus

Dac, Uart, Usb, Verilog, Ethernet, Can, Spi, Pcie, Analog IPs, systemverilog, EDA Tools, SVA, assertions, power-aware simulations, security IPs, SoC-level verification, eSPI, Cadence Xcelium, Uvm, UPF, PLLs, gate-level simulations, ADC, Synopsys VCS, low-power verification, functional coverage, I²C, constrained-random verification, Flash Memory, ARM-based microcontrollers