C
Lead Design Engineer
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Lead Design Engineer
Cadence Design Systems (India) Pvt LtdEarly Applicant
- Posted a month ago
- Be among the first 10 applicants
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
1. Proficient in Verilog coding and RTL design, data path designs,
2. Knowledge of RTL checks ex- LINT, SDC, CDC
3. Familiar with synthesis flow and timing constraints
4. Experience in writing Verilog testbench and running simulations.
5. Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
We're doing work that matters. Help us solve what others can't.
More Info
Key Skills
UCIe
RTL checks
data path designs
Verilog testbench
MIPI
synthesis flow
DPHY
About Company
Skills:
clocking , Arm, Trace32, Multimedia, Microprocessors, Computer Architecture, interconnect safety, Synthesis, Security, ARM Debug, Ace, RTL design flow, Verilog RTL coding, RISC-V, APB, Axi, Reset, ATB, BUS Protocols, Chip Assembly, LINT, RTL signoff tools, Serial Interfaces, cdc, ARM CoreSight ETM, IP Integration, Arm Cortex-M A R processor-based SoC debug infrastructure, External Bus Interfaces, RDC, System modes
Skills:
Verilog, C Programming, Verification EDA Tools, bare-metal programming, Microcontrollers, RTL simulations
Skills:
display , simulations , Usb, Pcie, Timing Constraints, UCIe, Verilog Coding, LINT, RTL checks, data path designs, cdc, Rtl Design, Verilog testbench, MIPI, synthesis flow, SDC, HDMI, DPHY
Skills:
Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA
Skills:
routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis