Matlab, Worst case identification, Monte Carlo analysis, Physical layout management, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, Post layout parasitic extraction, Schematic generation and simulation, Top level verification, Knowledge of device physics and process technologies, Block level modelling, Simulation data analysis, IC transistor level implementation, IC system partitioning and architectural tradeoff analysis, Power IC design, Signal grounding and routing tradeoffs, Die area optimization

variation analysis , monte carlo , Python, Perl, Tcl, FineSim, IR drop, yield analysis, ECC redundancy and repair strategies, multi-Vt, circuit simulation tools, scripting knowledge, CMOS analog digital circuit design principles, Pvt, low-power memory design techniques, memory compiler design and automation, ISO 26262 Safety compliance, silicon debug, power gating, EM checks, XA, FastSPICE, Spectre, Hspice, Memory Characterization, multi-Vdd

PCS, Perl, Python, Tcl, reusable verification infrastructure, PHY link protocols, UVM environment development, high-speed interface verification, Uvm, systemverilog, Ethernet MAC, functional coverage closure, Ethernet protocol compliance verification, packet processing, complex protocol debug, SerDes controller validation, SVA, error handling

Pll, compensation techniques, transistor capacitor matching, transistor level circuit design, EDA Tools, analog mixed signal design, SERDES, high-speed TX, noise analysis