Lead Design Engineer
Lead Design Engineer
CADENCEThis job is no longer accepting applications
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Be part of the Cadence Memory IP Group adn responsible for -
Be part of the Cadence Memory IP Group adn responsible for -
- Developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers
- Responsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low level APIs on Microcontrollers.
- Responsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.
- Responsible for collaborating with verification team to deduce firmware-hardware co-verification plan.
- Support debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)
- Support debugging issues on emulation and Silicon bring-up boards.
- 4-6 years of experience in developing bare-metal firmware for High-speed Serdes or Memory interface Physical Layer blocks.
- Good Knowledge C programming language for embedded software development and use of relevant IDE.
- Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
- Good knowledge of Shell/Perl/Python/TCL scripting
- Good debugging skills
- Good experience on Verification EDA Tools like simulators and waveform viewers
- Good communication Skill
More Info
Key Skills
Embedded programming languages
Waveform viewers
Low level APIs on Microcontrollers
Verification EDA Tools
Bare-metal programming
About Company
Skills:
power optimization , static timing analysis, Verilog, Uvm, place-and-route, Synthesis, SV-based testbenches, verification methodologies, power optimization techniques, Simulation, Timing Analysis, Cadence, coverage-driven verification, systemverilog, Rtl Design, VHDL, EDA Tools, Mentor Graphics, digital design flow, Synopsys
Skills:
Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA
Skills:
C, C++, Perl scripting, Tcl, Innovus, Calibre, primetime, ICC2, LEC, ICC, ICCII
Skills:
boundary scan , Perl, Scripting Languages, Python, Tcl, scan compression, JTAG IEEE 1149.1, Scan Insertion, memory BIST, DFT methodologies, DFT EDA tools, test pattern generation, ATPG, silicon bring-up, post-silicon debug, Cadence Modus Genus
Skills:
Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC