power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

Rcp, Rc, Tcl Scripting, Perl, low power design, Primepower, Sta, Constraints Signoff, DCG, PowerArtist, UPF, CPU micro-architecture, primetime, Synthesis, ASIC flow, Place and route tool understanding, DCT, CPF, high speed CPU implementation