Layout Design Engineer
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About the job
About the Company
SmartSOC Solutions is dedicated to delivering cutting-edge semiconductor solutions. Our mission is to innovate and excel in the field of advanced technology, fostering a culture of collaboration and excellence.
Qualifications
Responsibilities:
Job ID: 152031061
Skills:
layout verification , Ant, PERC, LPE, AI automation in layout, LEF generation, Cadence Virtuoso Layout suite, Siemens CALIBRE verification tools, SKILL Programming, EM, Analog Mixed-signal IP development, Ir, LVS, Dfm, PNR, Physical Design flow, ERC, DRC, Script Programming, FinFET layouts
Skills:
Automated PnR, High-speed SERDES IO PHY Layout design, Signal integrity issues, Analog IO design principles, CMOS and FinFET technologies, Block PnR
Skills:
Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs
Skills:
Electron migration, Analog layout design, Voltage drop, Process design rules, Signal planning, Micro-floor planning, High speed SerDes layouts, IR ESD, TSMC N3 technology, Design verification tools
Skills:
Cadence PVS, Mentor Calibre, tape-out, analog block integration, CMOS Circuits, BiCMOS circuits, Layout Design, Cadence Virtuoso, chip level integration verifications, debugging DRC
