layout verification , Ant, PERC, LPE, AI automation in layout, LEF generation, Cadence Virtuoso Layout suite, Siemens CALIBRE verification tools, SKILL Programming, EM, Analog Mixed-signal IP development, Ir, LVS, Dfm, PNR, Physical Design flow, ERC, DRC, Script Programming, FinFET layouts

Automated PnR, High-speed SERDES IO PHY Layout design, Signal integrity issues, Analog IO design principles, CMOS and FinFET technologies, Block PnR

Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs

Electron migration, Analog layout design, Voltage drop, Process design rules, Signal planning, Micro-floor planning, High speed SerDes layouts, IR ESD, TSMC N3 technology, Design verification tools

Cadence PVS, Mentor Calibre, tape-out, analog block integration, CMOS Circuits, BiCMOS circuits, Layout Design, Cadence Virtuoso, chip level integration verifications, debugging DRC