IP Verification Engineer
IP Verification Engineer
leadsoc technologies pvt ltd5-10 Years
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Job Description
IP Verification Engineer
Location: Bengaluru
Experience: 5–10 Years
Role Overview
We are looking for an experienced IP Verification Engineer to drive verification of ARM CPU subsystems and coherent interconnect architectures, with strong expertise in CHI coherency protocols and ARM subsystem debug/bring-up.
Key Responsibilities
- Develop and execute verification strategies for ARM CPU Subsystem (CPUSS) IPs.
- Verify AMBA CHI coherency and interconnect protocols, including functional and corner-case scenarios.
- Develop SystemVerilog/UVM testbenches, sequences, assertions, and functional coverage.
- Validate cache coherency, ordering, snoop transactions, data consistency, and error scenarios.
- Debug complex CPU subsystem, interconnect, and coherency failures across simulation and emulation.
- Support ARM subsystem bring-up, integration, and post-silicon debug.
- Drive regression, coverage closure, failure triage, and root-cause analysis.
- Collaborate with RTL, Architecture, Firmware, Emulation, and Silicon teams.
Core Technical Expertise
ARM CPUSS Verification | AMBA CHI | Coherency & Interconnect | SystemVerilog | UVM | Cache Coherency | Assertions | Functional Coverage | Subsystem Debug & Bring-up
Required Qualifications
- 5–10 years of hands-on IP/Sub-System verification experience.
- Strong experience with ARM CPU subsystem verification.
- Deep understanding of AMBA CHI and coherency concepts.
- Strong SystemVerilog/UVM verification skills.
- Experience debugging complex CPU/interconnect/coherency issues.
- Exposure to ARM subsystem integration, bring-up, emulation or silicon debug.
Preferred
- Experience with ARMv8/v9-based systems.
- Knowledge of ACE/AXI, cache hierarchy, snoop mechanisms, and memory ordering.
- Experience with simulation/emulation platforms and protocol checkers.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Functional Coverage
ARM CPU Subsystem Verification
Subsystem Debug Bring-up
Assertions
AMBA CHI
About Company
Skills:
Perl, Debugging, Python, Tcl, VPlan, Cadence simulators, Synopsys VC Formal, IP-level verification, JasperGold, Uvm, systemverilog, Testbench Architecture, Synopsys VCS, Axi, APB, AHB, root-cause analysis, performance verification
Skills:
Verilog, Pcie, SVA, formal verification, Assertions, Uvm, interconnect protocols, debugging complex RTL, systemverilog, CHI, AHB, Functional verification methodologies, Axi, testbench issues, Coverage
Skills:
Perl, Python, constraint-random testing, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog
Skills:
Python, Perl, Pcie, Uvm, JasperGold, LPDDR, VC Formal, CHI, Ace, GPUs, Verdi, Synopsys VCS, ARM CPU, Cadence Xcelium Simulator, DLA, HBM, Axi, Network on chip, AMBA protocols, ATB
Skills:
Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, Xcelium, Design Verification, QuestaSim, Uvm, systemverilog, Riviera, MIPI, Axi, APB, CXL, AHB, SoC Verification