Perl, Debugging, Python, Tcl, VPlan, Cadence simulators, Synopsys VC Formal, IP-level verification, JasperGold, Uvm, systemverilog, Testbench Architecture, Synopsys VCS, Axi, APB, AHB, root-cause analysis, performance verification

Verilog, Pcie, SVA, formal verification, Assertions, Uvm, interconnect protocols, debugging complex RTL, systemverilog, CHI, AHB, Functional verification methodologies, Axi, testbench issues, Coverage

Perl, Python, constraint-random testing, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Python, Perl, Pcie, Uvm, JasperGold, LPDDR, VC Formal, CHI, Ace, GPUs, Verdi, Synopsys VCS, ARM CPU, Cadence Xcelium Simulator, DLA, HBM, Axi, Network on chip, AMBA protocols, ATB

Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, Xcelium, Design Verification, QuestaSim, Uvm, systemverilog, Riviera, MIPI, Axi, APB, CXL, AHB, SoC Verification

Verilog, System Verilog, C, Python, Ovm, Perl scripting, VMM, Uvm, AHB, Axi