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The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
For nearly 50 years, AMD (NASDAQ: AMD) has driven innovation in high-performance computing, graphics, and visualization technologies the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses, and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work, and play.
Job ID: 114466205
Skills:
code coverage , Ovm, Vcs, Git, Perl, Test Plan Creation, Python, System Verilog, NLP simulations, verification closure, Formal Property Verification, non-NLP simulations, Uvm, GLS, testbench architecture, waveform debug, Design Verification, functional coverage
Skills:
Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, VHDL, Cadence Xcelium, Uvm, systemverilog
Skills:
C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools
Skills:
C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools
Skills:
C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM
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