code coverage , Ovm, Vcs, Git, Perl, Test Plan Creation, Python, System Verilog, NLP simulations, verification closure, Formal Property Verification, non-NLP simulations, Uvm, GLS, testbench architecture, waveform debug, Design Verification, functional coverage

Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, VHDL, Cadence Xcelium, Uvm, systemverilog

C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM

Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

Python, Perl, Pcie, Uvm, JasperGold, LPDDR, VC Formal, CHI, Ace, GPUs, Verdi, Synopsys VCS, ARM CPU, Cadence Xcelium Simulator, DLA, HBM, Axi, Network on chip, AMBA protocols, ATB

System Verilog, Vcs, DRAM memory controllers, Questa, Uvm, Xcellium, AXI4 bus protocol, Riviera, Vivado

Scripting (Perl/Python/Shell), SystemVerilog/UVM, DDR/LPDDR Protocols, Functional and Code Coverage, RTL Design and Debugging, Assertion-Based Verification, IP verification