We are seeking a highly skilled and motivated DRAM IP Validation Engineer to join our Hardware Engineering team. You will be responsible for ensuring the successful validation and integration of high-performance DRAM memory controllers and PHYs within complex SoC (System on Chip) devices. You will work closely with architecture, design, and verification teams to ensure top-tier memory performance.
Key Responsibilities
- Test Plan Development: Define and develop comprehensive functional test plans for DRAM/DDR IP (DDR4/DDR5/LPDDR).
- Validation Execution: Perform post-silicon validation of memory controllers and memory devices
- Debug & Root Cause: Analyse test results and approve test data for part approvals else, work with vendor teams to RCA the issue and conclude.
- Automation: Develop scripting tools (Python, Perl) to automate validation workflows.
Minimum Qualifications
- Education: BS/MS degree in Electrical/Electronics/Computer Engineering.
- Experience: 4+ years in DRAM/Memory controller validation or design verification.
- Languages: Python experience is preferred
- Technical Knowledge: Deep understanding of DRAM architectures, DDR4/DDR5/LPDDR protocols, and JEDEC standards.
Preferred Qualifications
- Experience with DDR PHY calibration and initialization software.
- Experience in post-silicon lab validation using high-speed oscilloscopes and logic analyzers.
