IP/Subsystem Verification Lead

THE ROLE: 

The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. 

THE PERSON: 

The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. 

KEY RESPONSIBILITIES: 

• Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
• Understand TestBench Architecture and develop expertise in TestBench Verification Components.
• Mentor junior engineers.

PREFERRED EXPERIENCE: 

• Proficient in IP or Sub-system level ASIC verification 
• Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar.
• Exposure to RTL design, software development, formal verification, or other related domains.
• Experience in UVM TestBench Development for complex designs preferred.
• Experience in RAL is preferred