GLS Verification Engineer
GLS Verification Engineer
smartsoc solutions pvt ltdThis job is no longer accepting applications
Job Description
Experience: 3–8 Years
Location: Hyderabad,
Key Responsibilities
- Execute Gate-Level Simulations (GLS) with zero-delay and SDF timing.
- Debug setup/hold, recovery/removal, X-propagation, and timing violations.
- Validate RTL-to-gate equivalence and synthesis/P&R impacts.
- Perform SoC-level GLS for boot, reset, clocks, interrupts, and functional scenarios.
- Verify low-power features such as UPF, isolation, retention, and level shifters.
- Validate DFT/scan/ATPG/JTAG functionality at gate level.
- Debug failures using VCS/Xcelium/Questa, Verdi/DVE and waveform analysis.
- Correlate GLS failures with STA, RTL, synthesis, PD, and DFT results.
- Automate GLS regressions using Python/Perl/Tcl/Shell.
- Support pre-silicon signoff and tape-out readiness.
More Info
Key Skills
About Company
Skills:
Vcs, Perl, Python, Tcl, Sta, Verdi, Gate-Level Simulation, reset clock-domain issues, RTL-to-netlist flow, Timing Concepts, Uvm, systemverilog, SDF annotation, X-propagation
Skills:
Verilog, Synopsys VCS, Cadence Xcelium, SDF annotation timing checks, Recovery removal checks, Setup hold analysis, Modelsim, Post-synthesis and post-layout netlist verification, systemverilog, Siemens QuestaSim
Skills:
Jenkins, Git, Gerrit, C-programming, X-propagation debug, GLS of large ASIC designs, Verdi on large designs