Vcs, Perl, Python, Tcl, Sta, Verdi, Gate-Level Simulation, reset clock-domain issues, RTL-to-netlist flow, Timing Concepts, Uvm, systemverilog, SDF annotation, X-propagation

Verilog, Synopsys VCS, Cadence Xcelium, SDF annotation timing checks, Recovery removal checks, Setup hold analysis, Modelsim, Post-synthesis and post-layout netlist verification, systemverilog, Siemens QuestaSim

Jenkins, Git, Gerrit, C-programming, X-propagation debug, GLS of large ASIC designs, Verdi on large designs