Functional Verification Engineer

Project Role : Functional Verification Engineer

Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

Must have skills : SoC Verification

Good to have skills : NA

Minimum 5 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary:

As a Functional Verification Engineer, a typical day involves developing and executing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly validate the design. Collaboration with design and architecture teams is essential to identify potential corner cases and guarantee complete functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across teams to maintain high-quality verification standards throughout the project lifecycle.

Roles & Responsibilities:

• Expected to be an SME, collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Lead efforts to define verification strategies and methodologies to improve overall quality and efficiency.
• Mentor junior team members by providing guidance and support to enhance their technical skills and project contributions.
• Coordinate with cross-functional teams to align verification goals with project timelines and deliverables.
  
  

Professional & Technical Skills:

• Must To Have Skills: Proficiency in SoC Verification.
• Strong knowledge of verification methodologies including constrained-random testing, directed testing, and coverage-driven verification.
• Experience with hardware description and verification languages such as SystemVerilog and Universal Verification Methodology.
• Ability to develop and maintain complex testbenches and verification environments.
• Familiarity with debugging tools and techniques to analyze simulation results and identify design issues.
• Understanding of digital design principles and architecture to effectively collaborate with design teams.
  
  

Additional Information:

• The candidate should have minimum 5 years of experience in SoC Verification.
• This position is based at our Bengaluru office.
• A 15 years full time education is required.