Coverage-driven verification techniques, SoC Verification, systemverilog, Simulation tools and methodologies for functional verification

Vcs, Shell, Perl, Verilog, Python, Incisive, Uvm, coverage-driven verification, systemverilog, VHDL, functional coverage closure, Questa

Developing Verification environments using System Verilog, Problem-solving and debugging, Verification and Design, UCIe domain, UVM methodology, Functional Verification