Lead and own the RTL verification of FPGA-based designs from concept to tape-out
Define and drive FPGA verification plans and testbenches (System Verilog/UVM).
Collaborate with design engineers to understand architecture and micro-architecture specifications
Perform functional coverage analysis, regression testing, and debug failures.
Mentor and lead verification engineers.
Domain Expertise
Experience with FPGA platforms such as Xilinx and Intel (Altera), including AXI-based design integration and verification of high-speed interfaces like PCIe, DDR, and Ethernet.
Skilled in developing verification IPs and performing validation on FPGA platforms.
Strong command of SystemVerilog, UVM, and industry-standard simulation tools such as QuestaSim and VCS.
Expertise in building self-checking verification environments using VHDL/Verilog, including BFMs, checkers, monitors, and scoreboards.
Solid understanding of HDL languages including Verilog, VHDL, and SystemVerilog.
Proficient in automation scripting using languages like Perl, Tcl, or Python.
