Job Description
Job Title: FPGA Developer (HFT Trading)
Location: Onsite – Hyderabad
Type: Full-Time
Reports To: Founder
About PHNX Securities
PHNX Securities is a next-generation quantitative trading firm focused on building systematic, research-driven trading infrastructure across global markets.
We design and deploy high-conviction, fully automated trading strategies with strict risk controls, robust backtesting frameworks, and clean execution systems.
We do not chase noise.We engineer precision.
At PHNX, we THINK, STRATEGIZE, BUILD, and TRADE.
Our Mission
To combine quantitative research, advanced hardware acceleration, automation, and disciplined risk management to build scalable, repeatable, and high-performance systematic strategies.
Role Overview
We are seeking an FPGA Developer to build and architect our ultra low latency execution platform from the ground up.
This is a founding technical leadership role. You will define the architecture of our FPGA-based trading stack for Indian exchanges (NSE, BSE), own execution performance, and lead low-latency software engineers.
This role is both strategic and hands-on.
You will shape the future of PHNX's execution infrastructure.
What You Will Do
• Architect and build an ultra-low latency trading stack using FPGA acceleration
• Lead a mixed FPGA + low-latency C++ engineering team
• Design exchange connectivity pipelines for NSE
• Optimize market data handling, order entry paths, and deterministic execution timing
• Define hardware/software partitioning strategy
• Implement latency measurement, monitoring, and deterministic risk checks
• Collaborate closely with quant researchers, traders, and risk teams
• Establish development standards, CI/CD, hardware testing, and deployment practices
• Own trading system risk controls within the FPGA and execution layer
• Drive performance benchmarking and continuous optimization
Who You Are
• 1+ years FPGA development experience in financial markets
• Deep understanding of ultra-low latency trading systems
• Experience leading technical teams or large-scale projects
• Proficient in VHDL, Verilog, or SystemVerilog
• Strong C++ experience in performance-critical systems
• Comfortable with Python for tooling and research integration
• Strong understanding of networking protocols (TCP/IP, UDP, multicast)
• Familiar with exchange protocols (ITCH, OUCH, FIX, native gateways preferred)
• Experience working with hardware timing constraints and deterministic systems
Bonus Points
• Experience optimizing sub-microsecond execution paths
• Experience in co-location environments
• Knowledge of kernel bypass (Solarflare, DPDK, Onload, etc.)
• Experience building OMS or risk engines
