FPGA Engineer
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RTL FPGA Design Engineer
Experience: 2 to 4 Years
Location: Hyderabad, India.
Job Description:
About Company
ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.
Job ID: 144751059
Skills:
transceivers , DDR, Verilog, Pcie, Tcl Scripting, VHDL, FPGA development, Questasim, FPGA hardware platforms, Rtl Design
Skills:
Embedded C, Verilog, Python, Axi, Vivado, Uvm, systemverilog
Skills:
Tcl Scripting, Vivado Quartus or Libero Tools, RTL Design using Verilog VHDL, Hardware Debugging and Board Bring-up, FPGA Design Flow Synthesis Implementation P R Timing Closure, High-Speed Protocols PCIe Ethernet DDR Transceivers, FPGA Design and Validation, CDC Clock Domain Crossing Analysis, Simulation using Questasim, FPGA Integration Experience, Experience using Oscilloscopes and Logic Analyzers, Static Timing Analysis STA
Skills:
microblaze , synplify , nios ii , Vcs, Shell, Verilog, Tcl, Ethernet, Python, Pcie, DDR, quartus, Questa, systemverilog, Lattice FPGAs, Vivado, Modelsim, VHDL, Xilinx, Intel Altera, ARM SoCs, Axi
