Search by job, company or skills

FPGA Design Engineer

FPGA Design Engineer

ALTEN Calsoft Labs
4-6 Years
Not Disclosed
Early Applicant
  • Posted a month ago
  • Be among the first 10 applicants

Job Description

Exp level:4+ years

Location: Hyderabad/Banglaore

Job Title:FPGA Engineer

Required skill for the Job:• Basic STA knowledge along with tools like Vivado.

• Experience on FPGA platforms like AMD(XILINX)/Altera.

• Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs

• Experience in scripting language like perl, python and tcl

• Working experience on Linux.

• Ensure to complete design and timing verification tasks within allotted timelines.

• Ability to work individually and in a team

Basic Job Deliverable:• Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification

• Perform task of debugging design timing related issues on different FPGA families

• Perform the work of manifold segmentation of the FPGA designs.

• Run internal scripts for performance testing and update scripts when necessary

Qualification:BTech/MTech

Interested can share CV to [Confidential Information]

More Info

Job Type:
Industry:
Function:
Employment Type:

Key Skills

About Company

Similar Jobs

4-10 yrs
Hyderabad, India
Skills:
Tcl Scripting, Vivado Quartus or Libero Tools, Experience using Oscilloscopes and Logic Analyzers, CDC Clock Domain Crossing Analysis, FPGA Design and Validation, High-Speed Protocols PCIe Ethernet DDR Transceivers, Hardware Debugging and Board Bring-up, Simulation using Questasim, RTL Design using Verilog VHDL, Static Timing Analysis STA, FPGA Design Flow Synthesis Implementation P R Timing Closure, FPGA Integration Experience
6-8 yrs
Hyderabad, India
Skills:
synplify , Vcs, Shell, Verilog, Python, Tcl, quartus, systemverilog, Lattice FPGAs, VHDL, Vivado, Questa, Intel Altera, Modelsim, Xilinx
7-9 yrs
Hyderabad, India
Skills:
Hdl Languages, Perl, Verilog, Python, Tcl, FPGA tools, quartus, VHDL, Vivado, systemverilog