Tcl Scripting, Vivado Quartus or Libero Tools, Experience using Oscilloscopes and Logic Analyzers, CDC Clock Domain Crossing Analysis, FPGA Design and Validation, High-Speed Protocols PCIe Ethernet DDR Transceivers, Hardware Debugging and Board Bring-up, Simulation using Questasim, RTL Design using Verilog VHDL, Static Timing Analysis STA, FPGA Design Flow Synthesis Implementation P R Timing Closure, FPGA Integration Experience

synplify , Vcs, Shell, Verilog, Python, Tcl, quartus, systemverilog, Lattice FPGAs, VHDL, Vivado, Questa, Intel Altera, Modelsim, Xilinx

Hdl Languages, Perl, Verilog, Python, Tcl, FPGA tools, quartus, VHDL, Vivado, systemverilog