Debugging, Scripting, formal verification, assertions, hardware micro-architecture, testplans

Verilog, Debugging, Automation Scripting, formal verification, AI-assisted Workflows, Protocol Verification, Property Checking, SVA, systemverilog, Equivalence Checking, Formal Analysis

Python, Jasper VC Formal, formal verification, Property-based FV, Formal Tools, SVA, Questa Formal

Shell, Python, Perl, formal verification technologies, complexity reduction techniques, high quality testplans, formal testbenches, root-causing counter-examples

Tcl, Python, Perl, PSL, JasperGold, OneSpin, VC Formal

Tcl, Python, Perl, Static Low Power Verification, Power Management library cells, Synopsys Formality