You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities.
KEY RESPONSIBILITIES:
- Work closely with the SoC Architecture and uArch teams to define the DFT architecture.
- Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up
- Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up
- Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models
- Work with the post-silicon team on debug support and to help root-cause any failures
- Be upto date with the industry trends and bring-in the latest to the AMD products
- Work with DFT Tool Vendors and drive improvements based on our requirements
REQUIREMENTS:
- 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes.
- Good understanding and exposure to SoC design and architecture
- Very good understanding of verif and timing concepts having handled DFT timing closure
- Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc
- Comfortable with VCS/Verdi and Mentor TK.
- Logical in thinking and ability to gel we'll within a team
- Good stakeholder management
- Ability to quickly adapt to changes and handle pressure
- Good communication and leadership skills
