Perl, Python, Tcl, LVS DRC violations, Timing area and power constraints, Block-level place and route, P R flow development, CAD and physical design methodologies, Clock network guidelines, Physical design verification, Logic equivalency RTL2Synthesis, Physical Design, Synthesis2APR netlist, PPA optimization

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

static timing analysis, PVT conditions, timing budgeting, timing rollups, Timing Analysis, timing constraint adaptation, clock network optimization, timing models

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure

Verilog, Tcl, ASIC design flow, low-power techniques, DFT Design for Test, UPF Unified Power Format, primetime, Synopsys Design Compiler NXT DCnext, Fusion Compiler, Formality, systemverilog, MCMM flows

Performance Analysis, Linux drivers, workload characterization, systemverilog, CPU GPU benchmark characterization, performance analysis tools, SOC design verification, runtime, mobile SOC performance model development

transactor development, UVM for verification, PnR runtime and debug, HVLs SV, SoC design and architecture concepts, SV for RTL design, Synthesis partitioning, HDLs Verilog, testbench mapping, PnR flows, multi FPGA prototyping flows, RTL synthesis, hardware software debug solutions related to FPGA prototyping, design mapping, ICE and co-model solutions, test bench acceleration, FPGA based hardware prototyping platforms, Functional Verification