Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Placement and Routing, Timing Closure, Physical Design Implementation

Routing, floorplanning, Power Planning, CTS, Place And Route, Placement

Electronic design automation tools, Physical Design, Design for manufacturability, Placement and routing methodologies, Clock Tree Synthesis, Design rule checks, Timing closure techniques

static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

Perl, Verilog, Python, Tcl, Synthesis, cdc, structural RTL analysis, Linux development environments, systemverilog, RDC, Timing Constraints, LINT, low-power verification

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

matching , layout verification , Mentor Graphic Calibre DRC, analog custom layout design, electro-migration, IR-drop, coupling, crosstalk, latch-up, advanced CMOS process, static device parasitics, Cadence VLE

Verification Tools, Cadence Virtuoso Layout Editor, Cadence LVS, Calibre RVE