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EDA Methodology & Application Engineer Spyglass & Morph tools

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  • Posted 13 days ago
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Job Description

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Role Overview

Your role and responsibilities

We are looking for a passionate and experienced EDA Methodology Engineer to join our Frontend EDA team, focusing on Spyglass lint checking using Synopsys Spyglass for CDC/RDC & IBM Morph tools for hierarchy transformation & aspect insertion. In this role, you'll work closely with design teams and EDA vendors to develop and implement robust verification flows that ensure structural correctness across design stages.

Key Responsibilities

  • Develop and maintain Spyglass CDC/RDC flows using Synopsys Spyglass.
  • Develop & support IBM Morph suite of tools used for hierarchy translation & aspect insertion like DFT, clock controller etc.
  • Collaborate with cross-functional teams to align verification methodology with design goals.
  • Drive methodology improvements for design verification.
  • Coordinate with internal stakeholders and external vendors to deliver high-quality solutions.

Preferred Education

Master's Degree

Required Technical And Professional Expertise

  • Bachelor's or Master's degree in Computer Science, Electronics Engineering, or VLSI Design.
  • 58 years of hands-on experience with Synopsys Spyglass.
  • Strong understanding of RTL design languages: VHDL, Verilog, SystemVerilog.
  • Expertise in Tcl and Python scripting.
  • Deep knowledge of Linting and structural checking on RTL designs.
  • Experience in setting up flows and running static CDC/RDC checks on RTL..
  • Proven ability to troubleshoot and resolve complex structural checking issues.
  • Strong communication and collaboration skills.

Preferred Technical And Professional Experience

  • Experience with Linting flows.
  • Familiarity with CDC/RDC linting methodologies in large-scale SoC projects.
  • Familiarity with DFT methodologies.

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About Company

Job ID: 142120741