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DV Lead
smartsoc solutions pvt ltd

DV Lead

smartsoc solutions pvt ltd
8-10 Years
Not Disclosed
  • Posted 18 hours ago
  • Be among the first 10 applicants

Job Description

Experience : 8+ Years SOC/IP.

Looking for an Senior/Lead ASIC Verification Engineer

experience in verification of IP/SOC.

• Must have experience in System Verilog, UVM, C.

• Ethernet/PCIe/Chi protocol knowledge

• Should have good debugging and analytical skills.

• Good to have Scripting knowledge (Python/Perl/shell).

• Good communication skills

• Hands-on experience in Front-end verification tools.

• Desirable to have knowledge of Power aware verification, GLS, Formal Verification.

Roles And Responsibilities

• Able to Lead and motivate the team within the constraints of tight schedules.

• Responsible for verifying the ASIC design, architecture and microarchitecture using advanced verification methodologies.

• You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

• Come up with test plans, tests.

More Info

Job Type:
Permanent Job
Industry:
Semiconductor Manufacturing
Function:
ASIC Verification
Employment Type:
Full time

Key Skills

Power aware verification

Chi protocol

Uvm
GLS

Front-end verification tools

formal verification
C
Pcie
Perl
Ethernet
System Verilog
Python
Last Updated: 09-10-2026 10:16:22 AM

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