cadence spectre , simvision , Hdl, shell scripting, Perl, Python, Tcl, Xcelium, Cadence Mixed-Signal Design Environment, verilogAMS, mixed-signal design verification, VIVA, SV RNM, Virtuoso ADE, Assembler, SV UVM

Perl, Python, Synopsys VCS, Siemens Questa, Verdi, Cadence Xcelium, DVE, Uvm, UPF, systemverilog

Regression management, Assertion-based verification, SystemVerilog UVM

Pcie, Ethernet, Emulation, hardware-assisted verification, ASIC SOC verification, NIC Cards, mixed-signal verification, UCIe, Uvm, gate-level simulation, coverage-driven verification, systemverilog, FPGA prototyping, high-speed SerDes, regression CI, formal verification, Cache-coherency verification, low-power UPF, constrained-random methodology, Verilog-AMS, performance-verification methodology, CXL, PAM4, FEC coding