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DV Engineer - Lead
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DV Engineer - Lead
astika software technologies private limitedEarly Applicant
- Posted 27 days ago
- Be among the first 10 applicants
Job Description
DV Engineer – Lead (10+ yrs) – Bangalore
Role - Design Verification Lead
Experience - 10+ Years
Location - Bangalore
Responsibilities
Role - Design Verification Lead
Experience - 10+ Years
Location - Bangalore
Responsibilities
- Lead verification strategy for complex SoC/IP blocks
- Own verification planning, coverage closure, and sign-off
- Mentor DV sub-leads and team members
- Develop UVM-based testbenches and reusable VIPs
- Drive bug triage and cross-functional collaboration with RTL teams
- SystemVerilog, UVM
- Functional & code coverage
- SoC-level verification
- Strong debugging and leadership skills
More Info
Key Skills
Functional code coverage
SystemVerilog UVM
SoC-level verification
About Company
Skills:
Perl, Python, Synopsys VCS, Siemens Questa, Verdi, Cadence Xcelium, DVE, Uvm, UPF, systemverilog