Job Requirements

Job Description

Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer

Location: Bangalore, Karnataka, India

Team: SoC Design Verification / Silicon Sign-off

Position Summary

We are seeking a highly skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon tape-out. In this critical role, you will be responsible for verifying the post-synthesis, final netlist of our complex SoCs, ensuring that the design's functionality remains correct after synthesis, placement, and routing.

You will hunt down the most subtle and challenging bugs related to timing, power, and reset that are invisible at the RTL level. The ideal candidate is a tenacious debugger with a deep understanding of digital design, simulation technology, and the patience to navigate complex gate-level netlists.

Key Responsibilities

Own and execute the complete GLS verification strategy for complex IPs and full-chip SoCs, from initial planning to final sign-off.
Bring up, maintain, and debug existing UVM/SystemVerilog testbenches in both zero-delay and back-annotated (SDF) timing simulation environments.
Debug complex test failures in the gate-level netlist, identifying root causes related to:
Timing-dependent race conditions and glitches.
Reset propagation and synchronization issues.
X-propagation bugs masked by optimistic RTL simulation.
Initialization failures of flops and memories.
Develop and maintain robust automation scripts (Perl, Python, Shell) to manage GLS regressions, parse massive log files, and generate actionable reports.
Verify critical Design-for-Test (DFT) logic, including scan-chain integrity, memory BIST, and JTAG controllers, at the gate level.
Conduct power-aware GLS using UPF to validate low-power structures such as isolation cells, level shifters, and power-gating sequences.
Collaborate closely with RTL design, Physical Design (PD), and DFT teams to rapidly triage, root-cause, and resolve GLS failures.

Required Qualifications

Bachelor's or Master's degree in Electrical/Computer Engineering or a related field.
8+ years of hands-on experience in ASIC verification, with a significant portion dedicated specifically to Gate-Level Simulation.
Proven expertise in running and debugging simulations on EDA tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Strong debugging skills using waveform viewers like Verdi or DVE, with the ability to trace signals through a gate-level netlist.
Excellent scripting skills in Perl or Python.
Solid understanding of the differences between RTL and GLS environments.

DV Lead Engineer