DV Engineer

Company Description Chiplogic Technologies (Chiplogic) is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML solutions. The organization provides high-quality, dependable services across the full semiconductor design lifecycle, from concept to silicon. Chiplogic also delivers turnkey system solutions, proof-of-concept (POC) implementations, and IoT system integrations. In the AI/ML domain, the company builds solutions around its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, offering innovative video and real-time analytics capabilities. Team members work in a technology-driven environment focused on cutting-edge hardware and intelligent systems.

Role Description Chiplogic Technologies is looking for experienced Design Verification Engineers with strong expertise in ASIC/SoC verification. The ideal candidate should have hands-on experience in SystemVerilog, UVM, functional verification, testbench development and debugging. Candidates with substantial SoC-level verification experience and C programming skills will be preferred.

Key Responsibilities

• Develop and maintain reusable testbenches using SystemVerilog and UVM.
• Understand design specifications and develop comprehensive verification plans and test scenarios.
• Perform functional verification at IP and SoC levels.
• Develop constrained-random and directed test cases.
• Debug simulation failures and perform root-cause analysis.
• Track functional and code coverage, and drive coverage closure.
• Work closely with RTL designers to resolve design and verification issues.
• Execute regressions and ensure verification quality before sign-off.
• Contribute to end-to-end SoC verification activities.

Mandatory Skills

• 4+ years of hands-on experience in ASIC/SoC Design Verification.
• Strong knowledge of SystemVerilog and UVM.
• Experience in testbench development and verification environment setup.
• Good understanding of functional coverage, assertions and constrained-random verification.
• Experience with simulation and debugging tools such as VCS, Xcelium or Questa.
• Strong debugging and problem-solving skills.

Preferred Skills

• Hands-on experience in SoC-level verification.
• Good programming knowledge in C/C++.
• Experience with AMBA protocols such as AXI, AHB and APB.
• Knowledge of SVA (SystemVerilog Assertions).
• Experience in subsystem integration and end-to-end verification.
• Familiarity with scripting languages such as Python, Perl or Tcl.

Candidate Requirements

• Minimum 4 years of relevant Design Verification experience.
• Strong hands-on experience rather than theoretical knowledge.
• Candidates with SoC-level verification and C programming experience will be given preference.
• Immediate joiners or candidates with a short notice period are preferred.