Usb, Debugging, DDR, Pcie, Ethernet, Uvm, Testbench development, Simulation Tools, systemverilog, MIPI, VIP integration, Coverage closure

Test Cases, Bug Tracking, Sequences, Uvm, scoreboards, concepts and methodologies, systemverilog, monitors, Drivers, functional coverage, simulation regression coverage analysis, UVM testbenches, verification plans

Tcl, Verilog, C, Python, Perl, Uvm, Zebu, Emulation, systemverilog, Palladium, Hybrid Simulation, Veloce

DDR, Pcie, Nvme, Verilog, System Verilog, scoreboard assertions, functional coverage coding, Axi, RTL debugging, Uvm, AHB, code coverage analysis

Vcs, Perl, Python, Tcl, Questa, Verdi, XSIM, AMBA protocols, Uvm, systemverilog, Axi, APB, DVE, AHB

Python, Perl, Shell, systemverilog, Uvm, Verilog-A, Verilog-AMS, Wreal, Cadence Virtuoso AMS Designer

assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification