EE graduate from a reputed school, with post-graduate qualifications preferred.
15+ years of industry experience in RTL design or verification using simulation-based technologies.
5+ years of experience managing medium to large-sized teams.
In-depth understanding of Assertion-based verification using formal and simulation methods.
Strong knowledge of hardware design (Verilog/VHDL) and micro-architecture.
Expertise in Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python).
Excellent oral and written communication skills.
Expertise in one or more areas such as Formal Property Verification testbench development, floating point arithmetic operations, C/C++, IEEE math libraries, Security architecture, Automotive Safety (FuSa) verification, and Verification signoff with formal.
