Director Design Verification

Director – Design Verification

Company:Scaledge Technology

Location:Bengaluru, Karnataka (On-site/Hybrid)

Experience:15+ years

Employment Type: Full-time, Permanent

About Scaledge Technolog

yScaledge Technology is a cutting-edge semiconductor company working on advanced AI connectivity and high-performance networking architectures. We're building next-generation SoCs and IPs for switches, NICs, and SmartNICs that power the future of data centers and AI infrastructure

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Role Overvi

ewWe're seeking an experienced Director of Design Verification to lead our verification organization and drive verification strategy for advanced SoC and IP projects. You'll build and mentor a high-performing DV team while establishing world-class verification methodologies for AI and networking chip design

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Key Responsibilit

iesLeadership & Strat

• egyDefine and own the overall verification strategy and roadmap for multi-year SoC/IP progr
• amsBuild, mentor, and lead a team of 20+ verification engineers across multiple proje
• ctsEstablish verification methodologies, processes, and best practices across the organizat
• ionCollaborate with RTL Architecture, Design, Software, and Product teams on verification plann
• ingDrive coverage closure and verification signoff for complex SoCs (Switches, NICs, SmartNI

Cs)Technical Excelle

• nceBuild and optimize block-level, subsystem-level, and system-level verification environme
• ntsOversee development of UVM/SystemVerilog testbenches, checkers, and coverage mod
• elsLead verification infrastructure development (testbenches, automation, regression framewor
• ks)Ensure robust verification for high-performance systems (Packet processing, RDMA, Ethernet, PCIe, M
• AC)Guide use of formal verification, emulation, and FPGA prototyping where applica

bleCross-functional Collaborat

• ionPartner with architecture teams on feature specification reviews and verification plann
• ingWork closely with software teams on validation interfaces and bring-up supp
• ortCoordinate with design teams on RTL quality, bug fixes, and iteration cyc
• lesInterface with clients and stakeholders on verification milestones and deliverab

lesRequired Qualificati

onsEducation & Experie

• nceB.Tech/M.Tech/PhD in Electrical Engineering, Computer Engineering, or related fi
• eld15+ years of experience in ASIC/FPGA verificat
• ion5+ years in leadership roles managing DV te
• amsProven track record of delivering verification for complex SoCs from spec to tape-

outTechnical Ski

• llsExpert-level proficiency in SystemVerilog and UVM methodol
• ogyStrong experience with networking architectures (Switches, NICs, SmartNI
• Cs)Deep knowledge of packet processing, RDMA, Ethernet, PCIe, MAC protoc
• olsExperience with high-performance, low-power, and advanced node designs (7nm, 5nm, 3
• nm)Hands-on experience with verification tools (VCS, Xcelium, Verdi, Questa, Cadence P
• IE)Scripting expertise in Python, Perl, Tcl, or Shell for automat
• ionKnowledge of formal verification, emulation (Zebu/Palladium), and FPGA prototyping is a p

lusLeadership Ski

• llsProven ability to build and scale high-performing DV te
• amsStrong mentorship skills with experience grooming senior engineers and manag
• ersExcellent communication skills for cross-functional collaboration and client interact
• ionStrategic thinking with ability to balance technical depth and organizational vis