static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Scripting, Static Timing Analysis, Routing, Design Compiler, CTS, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, RTL to GDS2 flow, Floor-plan Physical Implementation, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

Rtl Design, Physical Verification, DPT Optimization, Timing Closure, Place And Route

AWS, Networking, Itil, Azure, Servicenow, Gcp, hybrid infrastructure models, Synopsys, HPC environments, Siemens EDA, EDA Tools, cloud platforms, compute storage grid, Cadence, Scheduling, SRE practices

Usb, Spi, Silicon Validation, Pcie, Scripting, design automation tools, Design Verification, RTL, Dft, Physical Design, MCU design, DMA, software validation

static timing analysis, Verilog, Synthesis, SoC integration, design constraints, embedded CPUs, IP integration, systemverilog, Rtl Design, ML AI accelerators, Axi, BUS Protocols, clock power reset domains, low-power design techniques, AHB

C, Python, Soc Architecture, coherency protocols, validation automation frameworks, interconnects, DFT infrastructure, Linux-based environments, debug tools, power management

Networking, Itil, AWS, Servicenow, Azure, Gcp, Synopsys, hybrid infrastructure models, HPC environments, Siemens EDA, EDA Tools, cloud platforms, compute storage grid, Cadence, Scheduling, SRE practices