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Company Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
This is an opportunity to join a top-notch Power Design Team within Renesas Electronics America's leading power management product line. As part of one of Renesas's most prominent consumer and industrial Design Groups, this director will work on next-generation IC products for multiple fast paced consumer, industrial and automotive power products.
Job Description
Job Responsibilities
Qualifications
Job Requirements
Job ID: 151205537
Skills:
IC design, Packaging requirements, Design IP process technology, Power management design, Verification
Skills:
Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft
Skills:
production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design
Skills:
Peripheral subsystems, Assertions, UVM-based test plan development, HSIO, SoC-level verification, Integration of multiple IPs, Verification infrastructures, coverage analysis
Skills:
Eda, Machine Learning, Artificial Intelligence, automation, physical implementation, extraction and simulation workflows, generative AI, design migration and design reuse, analog and custom IC design, LVS, OpenAccess-based design environments, semiconductor design, Physical Verification, circuit simulation SPICE, DRC, Parasitic Extraction, analog verification flows, standard cell design and optimization, Cadence Virtuoso