IC design, Packaging requirements, Design IP process technology, Power management design, Verification

Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Peripheral subsystems, Assertions, UVM-based test plan development, HSIO, SoC-level verification, Integration of multiple IPs, Verification infrastructures, coverage analysis

Eda, Machine Learning, Artificial Intelligence, automation, physical implementation, extraction and simulation workflows, generative AI, design migration and design reuse, analog and custom IC design, LVS, OpenAccess-based design environments, semiconductor design, Physical Verification, circuit simulation SPICE, DRC, Parasitic Extraction, analog verification flows, standard cell design and optimization, Cadence Virtuoso