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Digital Design Engineer
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Digital Design Engineer
Nxp SemiconductorsThis job is no longer accepting applications
Job Description
- Strong digital design capabilities with 5+ years of proven experience in IP and subsystem design for MPU & MCU based products
- Proven experience in Security & Crypto IP and Subsystems development is preferable
- Experience in optimizing designs for low power and implementation of security countermeasures meeting functional / performance requirements defined in high level security architecture
- Good understanding of SoC functional & security architecture requirements, design integration requirements like CDC, RDC, Lint, DFT & low power for optimal IP design
- Responsible to work with IP architects, Verification engineers to debug and resolve issues reported in IP/subsystem/SoC integration of IPs
- Excellent communication skills, good team player to work with cross functional & global teams across the world with clear focus on delivering on time, quality and problem solving to come up with best-in-class Security IP designs,
More Info
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Key Skills
RDC
Security Crypto IP
SoC functional security architecture
security countermeasures
subsystem design
design integration requirements
About Company
Skills:
Verilog, System Verilog, Digital Logic Design, Synthesis, Pre-Silicon Verification, Post-Silicon Support
Skills:
UNIX, Debugging, Verilog, ASIC SoC design methodologies, systemverilog, design quality checks, RTL Coding, RTL integration, Windows environments, Ms Office Tools, Digital Design, Simulation, SoC connectivity concepts
Skills:
Firmware Development, FPGA Design, Verilog, Static Timing, ASIC design flow, Synthesis, datapath timing analysis, digital design principles, high-speed data transmission, systemverilog, CMOS digital circuits, Rtl Design, Dft, front-end tools, mixed signal concepts, Verification, clock design
Skills:
boundary scan , Perl, Scripting Languages, Python, Tcl, scan compression, JTAG IEEE 1149.1, Scan Insertion, memory BIST, DFT methodologies, DFT EDA tools, test pattern generation, ATPG, silicon bring-up, post-silicon debug, Cadence Modus Genus
Skills:
Vcs, Perl, Verilog, System Verilog, Python, Tcl, LINT, cdc, Xcelium, spyglass, RDC, Questa, Questa CDC