Digital Design Engineer

Company Description

Chiplogic Technologies, founded in 2018, specializes in providing high-quality IP and Product Engineering Services in Semiconductor, Systems, IoT, and AI/ML domains. With expertise in delivering dependable design and system solutions, Chiplogic supports clients from concept to silicon, including proof-of-concept (POC) and IoT system development. The company leverages its proprietary VISARD™ framework for advanced video synthesis and real-time dynamics in AI/ML initiatives.

Role Description

Chiplogic is looking for experienced Senior Digital Design Engineers with strong hands-on expertise in PCIe Gen6 or Gen7 protocol development for advanced ASIC/SoC designs. The ideal candidate should have solid experience in RTL Design, micro-architecture development, and integration of high-speed interface protocols in complex semiconductor environments.

Key Responsibilities

• Develop RTL design and micro-architecture for PCIe Gen6/Gen7 based subsystems and controllers.
• Work on high-speed protocol development involving PCIe, LTSSM, PIPE, DMA, and controller architectures.
• Perform RTL coding using Verilog/SystemVerilog with focus on power, performance, and area optimization.
• Collaborate with architecture, verification, physical design, and firmware teams for seamless SoC integration.
• Debug and resolve design issues related to functionality, timing, protocol compliance, and performance bottlenecks.
• Participate in design reviews, code reviews, and technical discussions.
• Support synthesis, lint, CDC, low-power checks, and silicon bring-up activities.
• Analyze and debug RTL and integration issues during simulation and post-silicon validation.

Required Skills

• Strong hands-on experience in RTL Design and Micro-architecture development.
• Expertise in PCIe Gen6 and/or Gen7 protocol architecture and implementation.
• Strong understanding of:
• PCIe LTSSM
• PIPE Interface
• Transaction/Data Link/Physical Layers
• DMA and Controller Architectures
• High-speed serial interfaces
• Proficiency in Verilog/SystemVerilog.
• Experience with ASIC/SoC design methodologies and integration flows.
• Good understanding of synthesis, timing closure, CDC, and lint methodologies.
• Familiarity with EDA tools from Synopsys/Cadence/Siemens.
• Strong debugging and analytical skills.

Preferred Qualifications

• Experience with CXL, NVMe, or other high-speed protocols is an added advantage.
• Exposure to advanced technology nodes such as 5nm/3nm is preferred.
• Knowledge of low-power design techniques and UPF is a plus.
• Prior experience in Datacenter, AI/ML, Networking, or Client SoCs preferred.

Educational Qualification

• Bachelor's or Master's degree in Electronics/ECE/VLSI/Microelectronics or related field.

Why Join Chiplogic

• Opportunity to work on next-generation PCIe Gen6/Gen7 technologies.
• Exposure to cutting-edge semiconductor and high-performance computing projects.
• Collaborative engineering environment with strong technical growth opportunities.