DFT Solutions, Analog Mixed Signal IP IC, RTL Digital Design, Cost Analysis, Digital IP Wrapper, Architecture Feasibility, Methodology Quality Matrix

Fpga, Verilog, System Verilog, I2c, Simulation Tools, Digital Design, cdc, RTL Coding, Memory Architecture, audio signal chain, Cadence, VHDL, TDM, LINT, constraint development, Synthesis, ASI, digital timing analysis, RDC

STA (Static Timing Analysis), Shell/Perl/Python/TCL scripting., Verilog, Vcs, Lint/CDC/RDC checks, Synthesis flow, asic digital design engineer

Verilog, Python, Vlsi, Micro-architecture, Signal Processing, RTL

Rtl Design, Cross-functional integration, Verification strategy, system modeling, Mixed-signal verification, Simulink, Discrete-time filter design, Behavioral models, Power converter control, Fixed-point DSP implementation