DFT

boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST

Vcs, Static Timing Analysis, ATPG tools, Verdi, DFT ATPG, FSDB, Debug skills, Scripting skills, Synopsys Tetramax, Scan Patterns, Timing Closure, Siemens, Mentor Graphics, ATPG scripts

Debugging, occ, ICL, Dft, DRC coverage, pdl, Scan ATPG, Simulation, IJTAG, SSN

Verilog, Scan Insertion, ATPG, systemverilog

debug validation on automatic test equipment, Algorithmic Test Pattern Generation, fault modeling, silicon bring-up, ASIC DFT synthesis, Scan ATPG, MBIST, STA simulation and verification flow, DFT Design for Test technologies, DFT specification and definition, IP integration