boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST

Vcs, Static Timing Analysis, ATPG tools, Verdi, DFT ATPG, FSDB, Debug skills, Scripting skills, Synopsys Tetramax, Scan Patterns, Timing Closure, Siemens, Mentor Graphics, ATPG scripts

Debugging, occ, ICL, Dft, DRC coverage, pdl, Scan ATPG, Simulation, IJTAG, SSN

Verilog, Scan Insertion, ATPG, systemverilog

debug validation on automatic test equipment, Algorithmic Test Pattern Generation, fault modeling, silicon bring-up, ASIC DFT synthesis, Scan ATPG, MBIST, STA simulation and verification flow, DFT Design for Test technologies, DFT specification and definition, IP integration

logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, BSDL, Pattern simulation, Post Silicon debug analysis, DFT architectures, IDDQ, Chip level DFT, Fault Models, ATPG Pattern generation, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, stuck at, scan patterns and coverage statistics

boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

bist , Jtag, Python, Perl, Uvm, SV, Memory BIST, ATPG, NVIDIA custom tools