DFT Static Timing Lead

Will have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Implementation and verification of DFT architecture and features in NBIO IP and Subsystems
• Scan Network, Memory BIST logic generation and implementation
• Create and maintain DFT timing constraints
• Collaborate with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning
• Mentor and coach junior engineers

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST, HS IO Loopback, etc.)
• Experience with DFT Integration, Verilog RTL design
• Experience with DFT timing constraints and STA tools (Primetime)
• Pre-Silicon test planning & verification strategy
• Knowledge & experience of low power concepts, clock gating, power gating is a plus
• Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues
• Good communication skills
• Good script skills including perl, tcl, python, etc.
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization
• Must have good communication skills and the ability to work in a worldwide team environment